1. Field of the Invention
The present invention generally relates to the field of semiconductors, and more particularly relates to extremely-thin silicon-on-insulator field-effect transistors having extremely-thin silicon layers, and a method of fabricating the same.
2. Background Art
In order to be able to make integrated circuits (ICs), such as memory, logic, and other devices, of higher integration density than currently feasible, one has to find ways to further downscale the dimensions of field effect transistors (FETs), such as metal-oxide-semiconductor field effect transistors (MOSFETs) and complementary metal oxide semiconductors (CMOS). Scaling achieves compactness and improves operating performance in devices by shrinking the overall dimensions and operating voltages of the device while maintaining the device's electrical properties. Additionally, all dimensions of the device must be scaled simultaneously in order to optimize the electrical performance of the device.
With conventional planar FET scaling reaching fundamental limits, the semiconductor industry is looking at more unconventional geometries that will facilitate continued device performance improvements. As a result, attention has been given to using FETs with extremely thin silicon layers where the silicon or “device” layer has a thickness of from about seven run and about ten nm. When used with FETs having silicon on oxide, these devices are referred to as extremely thin silicon on oxide (ETSOI) devices. Extremely thin silicon layer technology can also be used with bulk wafers.
ETSOI devices have very substantial advantages, however they also present difficult challenges. For instance, these devices can experience threshold-voltage and subthreshold slope fluctuation because of Si thickness variations across the wafer. For example, a typical SOI device may have a silicon layer thickness of from 4-8 nanometers (nm), with a variation of 1 or more nm across the wafer.
Also, it has been determined that when implanting dopants into semiconductor layers that have a thickness of 10 nm or less, the ion implantation amorphizes the semiconductor layer. Recrystallizing the amorphous semiconductor layer is difficult, because of the limited amount of crystal seed layer that is available in semiconductor layers having a thickness of less than 10 nm that have been ion implanted into an amorphous crystal structure. The presence of an amorphous semiconductor material in a semiconductor device results in the semiconductor device having a high external resistance. Further, the resistance of the semiconductor device is increased by defects in the semiconductor layer that are produced by ion implantation. The ion implantation may also damage the gate dielectric.